With recent progress in various aspects of active matrix (thin-film transistor) liquid crystal display technology, the proliferation of active matrix displays has been spectacular in the past several years. In an active matrix display, there is a gate comprised of one transistor or switch corresponding to each display cell in the matrix. An active matrix display is operated by first applying select voltages to a row electrode to activate the gates of that row of cells, and second applying appropriate analog data voltages to the column electrodes to charge each cell in the selected row to a desired voltage level.
Typically, active matrix liquid crystal displays include drive systems which drive analog data voltages to the column electrodes using column drivers. Multiple column drivers are used to support all of the rows in the display. For example, in a matrix display having pixel dimensions of 1024×768, there are actually 3072 subpixels or display cells per row (each pixel having a red subpixel, a green subpixel, and a blue subpixel). Accordingly, there may be up to eight column drivers needed for such a display, with each column driver preferably supporting 384 subpixels or display cells. Typically, each subpixel is represented by digital pixel data having a bit depth of six or eight bits. Bit depth indicates the number of bits available per subpixel to control the brightness of the red, green or blue displayed for that subpixel. Pixel depth may vary depending upon the drive system. Accordingly, in a conventional drive system, each column driver is loaded with at least 2304 bits (6 bits per subpixel×384 subpixels). Bits are all loaded into the column drivers sequentially over a single parallel bus line, such that each column driver is loaded one after the other.
Once all bits for 384 subpixels have been loaded into any one column driver, a digital storage register is used to hold the digital pixel data until all eight column drivers are loaded. After all eight column drivers have been loaded, the digital pixel data for each subpixel is converted into an analog red, green or blue signal. This is typically accomplished by using one digital to analog converter per subpixel in each column driver. Accordingly, each column driver is required to have 384 digital to analog converters. The converters may be eight bit or six bit converters depending upon the bit depth of the drive system. Thus, this requires a large number of digital to analog converters, with each converter occupying a significant amount of die space depending upon whether it is a six bit or eight bit converter. Moreover, in a conventional embodiment, the digital to analog converters are designed to all operate at the same rate such that all RGB analog signals are produced for all 384 subpixels at the same time. Accordingly, such designs are extremely difficult and highly expensive.
Once all column decoders have converted the digital pixel data for each subpixel into RGB analog signals, the analog signals are typically passed through a buffer in order to generate sufficient current for driving the column electrodes of an active matrix liquid crystal display.
FIG. 1 illustrates a conventional active matrix liquid crystal display drive system. As shown, the conventional system includes an active matrix liquid crystal display 100 having a resolution of 1024 pixels×768 pixels. The display is driven by gate modules 180a through 180d and column drivers 160 through 160h. Due to spatial limitations, FIG. 1 only shows column drivers 160a, 160b, 160c and 160h; however, it is understood that in a conventional drive system for driving a display of resolution 1024 pixels×768 pixels, eight column drivers are used, with each column driver supporting 384 subpixels or memory cells. As shown in FIG. 1, a timing controller 110 is coupled to each of the column drivers 160a through 160h through a parallel data bus line 150. The timing controller 110 is also coupled to each of the gate modules 180a through 180d for providing row voltages in order to activate the display cells in each row.
The timing controller 110 provides digital display data, for an image to be displayed, to the column drivers in the form of digital pixel data on a row by row basis. The digital pixel data is provided in parallel using the parallel data bus line 150. A master clock signal MCLOCK 112 is used to control the rate at which the digital pixel data is transferred over the parallel data bus line 150. The timing controller 110 receives digital display data, for an image to be displayed, from some external source one display row of information at a time and stores the information. The external source may be a hard disk drive in a computer, a CD-Rom drive, a flash memory card or some other appropriate external storage device. Alternatively, the external source may be consist of an intranet or the internet. The digital display data is received as digital pixel data. The timing controller 110 stores the digital pixel data in a memory array (not shown) within the timing controller. The timing controller 110 then transfers the digital pixel data out to the column drivers 160a through 160h, in parallel using the parallel data bus line 150 and the master clock MCLOCK signal 112. As each row of the image to be displayed is transferred out to the column drivers over the parallel data bus line 150, a next row of digital pixel data is received and stored in the internal memory of the timing controller 110.
Each pixel supports a red subpixel, a green subpixel and a blue subpixel. In most video display applications, each pixel has a six or eight bit pixel depth. This means that each red, green and blue subpixel requires six or eight bits, such that the parallel data bus line 150 must be 36 or 48 bit lines wide. This is because the digital pixel data is typically transferred over the parallel data bus line 150 two pixels at a time—i.e. two pixels per MCLOCK pulse at a clock rate of 65 MHz for six bit pixel depth applications. Accordingly, in the prior art drive system illustrated in FIG. 1, the parallel data bus line 150 is shown as a thirty-six bit bus line, which transfers two eighteen bit pixels at a time (R0 (5:0), G0 (5:0), B0 (5:0)) and (R1 (5:0), G1 (5:0), B1 (5:0)) per MCLOCK signal pulse at a clock rate of 65 MHz.
Each of the column drivers 160a through 160h is coupled to the parallel data bus line 150. In the prior art, the column drivers 160a through 160h are loaded with the digital pixel data sequentially, receiving two pixels at a time. Accordingly, in the prior art drive system of FIG. 1, the first column driver 160a is loaded with digital pixel data from the controller 100 until all 384 subpixels have been loaded into the first column driver 160a. A shift register or some other appropriate device is preferably used to track the loading process. Once the first column driver 160a has been fully loaded, an enable signal 165 is then activated from the first column driver 160a to the second column driver 160b, thereby allowing the second column driver 160b to begin downloading digital pixel data from the parallel data bus line 150. Again, the second column driver 160b includes a shift register or some other appropriate device to track the loading process. Once the second column driver 160b has loaded all 384 subpixels, its enable signal 165 is activated from the second column driver 160b to the third column driver 160c, thereby allowing the third column driver 160c to begin downloading digital pixel data from the parallel data bus line 150. This process continues until all of the column drivers have been loaded.
Once all of the column drivers 160a through 160h have been loaded. The timing control sends a load signal 115 to each of the column drivers 160a through 160h instructing them to begin converting the digital pixel data for each subpixel into analog red, green or blue signals. The digital pixel data for each subpixel in the column drivers 160a through 160h is then converted into an analog voltage. This is accomplished by loading each subpixel into a digital to analog converter. The load signal 115 from the timing control instructs all of the column drivers to load each subpixel into the digital to analog converter. Thus, each column driver 160a through 160h requires 384 different digital to analog converters in order to convert each subpixel into a red, green or blue analog signal. Accordingly, in the prior art embodiment illustrated in FIG. 1, each digital to analog converter must be a six bit converter and the conversion of each subpixel from digital pixel data to an analog signal occurs after all the column drivers have been loaded and the timing controller 110 has sent the load signal 115. It is understood that although the embodiment illustrated in FIG. 1 shows a six bit depth per subpixel, the prior art may also typically use an eight bit pixel depth, thereby requiring 384 eight bit digital to analog converters (one for each subpixel).
After the digital pixel data for each subpixel has been converted into an analog signal, each of the analog red, green and blue signals are then passed through a buffer, in order to generate sufficient current levels, and applied to the column electrodes on an entire row basis. Thus, all red, green and blue analog signals for each subpixel in a row are applied to the column electrodes at the same time so the entire row is displayed in synch. The entire process illustrated above is repeated on a row by row basis until the entire image to be displayed has been transferred, converted, and displayed.
FIG. 2 illustrates a functional block diagram of a conventional column driver 160. As shown, the conventional column driver 160 includes a data register 200, for loading the digital pixel data from the parallel data bus line 150, and a shift register 210 for keeping track of the loading process. The conventional column driver 160 also includes a separate hold register 220 for holding the 384 subpixel data once the complete row data for that particular column driver has been loaded from the parallel data bus line 150. In this way, the conventional column driver 160 can continue to sample digital pixel data for a next row in the display while it processes the 384 subpixel data received for the current row.
Digital pixel data is loaded into the data register 200 of the column driver in parallel 36 bits or two pixels at a time. The shift register 210 is preferably a 64 stage shift register. Each time 36 bits or two pixels are loaded into the data register 200 of the column driver, the shift register 210 increments one stage. Accordingly, as the first 36 bits or two pixels are loaded in parallel from the parallel data bus line 150, into the data register 200, the shift register 210 increments one stage. As the next 36 bits or two pixels are loaded in parallel into the data register 200, the shift register 210 increments another stage. When all 128 pixels have been loaded into the data register 200, the shift register 210 increments to a final 64th stage, thereby triggering the column driver 160a to send an enable signal 165 to the next column driver 160b 420 so that the next column driver 160b can begin downloading digital pixel data from the parallel data bus line 150.
Once all 128 pixels have been loaded into the data register 200, the timing controller 110 sends a load signal 115 to the hold register 220, and all 128 pixels are transferred to the hold register 220, in parallel, for holding. In this way, once the last column driver 160h has been fully loaded, the first column driver 160a can once again begin downloading digital pixel data from the parallel bus line 150 into its data register 200.
A conventional column driver further includes 384 digital to analog converters (one for each subpixel). Once all of the digital pixel data for each subpixel in the complete row has been loaded into all the column drivers 160a through 160h, each six bit subpixel (red, green and blue) is converted within each column driver 160a through 160h into an analog red, green or blue signal which is then buffered and driven to the column electrodes of the display. Accordingly, each column driver requires 384 digital to analog converters, one for each subpixel, and the converters may be six bit or eight bit converters (depending upon the bit depth of the particular drive system involved). After all of the digital pixel data in all column drivers have been converted into analog signals, the analog red, green and blue signals are buffered in order to generate sufficient current and driven to the column electrodes of the display.
Typically, one row of data is provided in 16 μsec one pixel at a time at a pixel rate of 65 MHz or two pixels at a time at a pixel rate of 32.5 MHz. This 16 μsec is divided between the column drivers since each column driver receives digital pixel data sequentially—i.e. after the previous column driver has received all of its digital pixel data and the enable signal has been activated. Accordingly, as one can see, the amount of time required to transfer the data to each column driver and convert the data into analog voltages is limited. As active matrix displays become larger, the implementation and performance of the drive system becomes increasingly difficult to design. The number of column drivers is increased and the amount of time it takes for data to be loaded into each column driver and converted to analog signals is decreased, such that the drivers must perform faster as the number of pixels or display resolution increases.
Accordingly, what is needed is a more efficient system and method for driving an active matrix liquid crystal display such that as the number of pixels or display resolution increases, the system and method continues to perform efficiently.